1. Field of the Invention
The invention relates generally to the signal processing, and more particularly to signal processing in wireless communications.
2. Discussion of the Related Art
Wireless Local Area Network (WLAN) technology based upon Orthogonal Frequency Division Multiplexing (OFDM) is increasingly gaining in popularity due to very high spectral efficiency and extremely high data rates (e.g. 54 Mbits/second for IEEE 802.11a). The physical layer for OFDM-WLAN systems requires the implementation of FFTs (Fast Fourier Transform) for demodulation, complex division of the OFDM symbol for nominal channel estimation, and complex multiplication for channel equalization and pilot phase correction, all of which must be performed at high speed. The implementation of FFTs and vector-based complex operations necessitates very high computational throughput for the modem signal processing. However, the desire to implement systems with minimal cost, size, and power for VLSI implementation is constraining the performance capabilities.
One example of this is shown in a current system (FIGS. 1A and 1B) which requires data 103, 104 to be inputted into and outputted 104, 105 from two distinct processing stages 100, 101. As shown in FIG. 1B, this implementation requires two storage registers 106, 107, an adder/subtractor module 114, a multiplier module 113, two multiplexers 111, 112, and two counters 108, 109 in a processing stage. The storage registers 106, 107 combined may store the elements of a matrix as each is computed. The need for each of these hardware components and others necessary to tailor the system to a specific need keeps the hardware from becoming smaller in size without at the same time reducing computational power. Also, the need to keep the system small enough for a VLSI implementation prevents existing systems from being able to process a large number of operands.